1. Field of Invention
An exemplary embodiment of the present invention relates to techniques of coupling asynchronous circuits onto a synchronous circuit driven by a global clock. More particularly, an exemplary embodiment of the present invention relates to interface circuits to connect an asynchronous circuit to a synchronous circuit, and also relates to electronic devices including the asynchronous circuits, synchronous circuits and the interface circuits.
2. Description of Related Art
It is a minimum requirement for related art synchronous circuits to settle into the next state within a clock cycle. This means that, in the critical path, the sum of switching delays of sequential circuits and the setup time of a combination circuit must be sufficiently smaller than a clock cycle at the nominal voltage and temperature. The same requirement must be met when an asynchronous circuit block is embedded into a synchronous circuit system. If the requirement is not satisfied due to the delay in response of the asynchronous circuit block, the asynchronous circuit block needs to be redesigned or the frequency of the global clock needs to be lowered. The above is disclosed in U.S. Pat. No. 5,063,536.